This invention relates generally to the field of micro-electronics, and more specifically to a method for forming a sub-micron sized interconnect on a semiconductor wafer, and specifically to an improved etching procedure for avoiding the formation of a notch in a metal layer masked with a photoresist layer having a thickness of no more than 0.66 microns.
There is a continuing demand in the semiconductor industry for lower cost and improved reliability. The ability to create semiconductor devices with sub-micron sized features has greatly reduced the cost and improved the reliability of current devices when compared to similar devices produced just years ago. Smaller features result in a decrease in performance degrading capacitances and resistances and allow more devices to be formed on a single semiconductor wafer. However, the continued reduction in the size of the interconnections between the various active devices on a semiconductor wafer (interconnects) can result in an adverse electrical effect. Although the resistance of metal interconnects is reduced by a decrease in the length of the metal run, a reduction in the width and/or thickness of the interconnect structure will result in a corresponding increase in resistance per unit length, as well as an increased risk of electo-migration failures due to the higher current density carried by the narrower, thinner metal line. Thus, the designer of a very large scale integration (VLSI) device must carefully balance the advantages and disadvantages of continued reduction of the interconnect dimensions.
Continued reduction of dimensions in semiconductor devices have been made possible, in part, by advances in lithography, such as the use of more advanced cameras and the development of more sensitive photoresist materials. However, the accuracy of the lithographic pattern must then be reproduced onto the semiconductor. The use of reactive ion etching (RIE) has allowed the industry to transfer very small images in photoresist to an underlying metal layer. RIE removes material by exposing a surface to a combination of chemical etchants and a stream of plasma ions. In order to control the slope of the resulting metal layer side surface, it is desirable to have as thin a layer of photoresist as possible, limited however, by the relative removal rates of the masking photoresist and the exposed metal layer.
FIG. 1 illustrates a prior art semiconductor device 10 at a selected stage of a manufacturing process. Device 10 includes a semiconductor wafer such as silicon (Si) wafer 12 having an active device region such as silicon dioxide (SiO2) layer 14 formed therein. A metal layer such as aluminum copper (AlCu) layer 16 is disposed over the silicon dioxide layer 14, and is shown in FIG. 1 has having been partially removed by etching to form an interconnect structure 18. The width of interconnect 18 is defined by the width W of a photoresist layer 20 disposed over the metal layer 16. The aluminum copper layer 16 is separated from the silicon dioxide layer 14 by a titanium (Ti) layer 22 disposed on the silicon dioxide layer 14 and a first titanium nitride (TiN) layer 24 disposed on the titanium layer 22. In order to eliminate problems associated with back reflection of light during the photo-lithography process, it is known to form an anti-reflective coating (ARC) layer between the photoresist layer 20 and the metal layer 16. A second titanium nitride layer 26 and a layer of silicon oxy-nitride (SiON) 28 interact to function as an anti-reflective coating layer 27.
The materials and dimensions of device 10 and the processes used to manufacture such a structure are known in the art. For example, the aluminum copper material of metal layer 16 may range from about 0-1% copper, and may be deposited by known processes such as physical vapor deposition (PVD) to a thickness from 5,000-7,000 Angstroms. The titanium and titanium nitride barrier layers 22,24,26 may be deposited by PVD or chemical vapor deposition (CVD) to a thickness of 300-500 Angstroms. The ARC layer 28 may be deposited by CVD or plasma enhanced CVD to a thickness of 300-350 Angstroms. Portions of the barrier layers 28,26,24,22 and metal layer 16 are removed by an RIE process to form the interconnect 18 corresponding to the pattern formed in the photoresist layer 20.
A prior art recipe 40 for an RIE process for forming interconnect 18 is illustrated in FIG. 2. The recipe 40 includes the various steps shown in column 42 in the order taken, along with the respective flow rates of etchant gasses Cl2, BCl3, and passivation gas CHF3 shown in scc/min in the respective columns 44,46,48. The gas pressure present in the reactor during the respective step is shown in millitorr units in column 50. The source power and bias power applied during the respective steps are shown in watts in columns 52,54 respectively. The pressure of helium cooling gas supplied to the reverse side of the wafer 12 is shown as a constant 10 torr in column 56. Finally, the duration of each respective step is shown in seconds in column 58.
As shown in FIG. 2, the prior art RIE process begins with an etch step 6010 lasting thirty seconds for removing the ARC layer 27. The Cl2 gas acts as the etchant as the layers of material 28,26 are removed by high energy ions. The flow of CHF3 acts as a passivation gas during this step. Passivation is a concept known in the art for depositing a buffer layer on the surfaces of a material being exposed to a reactive ion etch. As the horizontal surface of the material is removed by the combination of chemical and sputtering effects generated by the vertically oriented ions produced in the RIE process, the newly exposed side vertical surface is protected from the ion stream by the overlying masking layer. However, the newly exposed vertical surfaces continue to be exposed to the effects of the chemical etchants. This isotropic chemical effect results in the undesirable removal of material in the horizontal direction during the desirable removal of material in the vertical direction. Passivation gasses supply a layer of protective material to the newly exposed vertical surfaces to retard the isotropic effect, thereby limiting the removal of material in the horizontal direction. A common passivation gas is CHF3 which is generally understood to provide a source of carbon that is deposited on the vertical surfaces of the metal layer being etched and which serves as a buffer against the continued corrosion of material in the horizontal direction. Without such passivation, an etched metal line may form as a trapezoid rather than the desired rectangular cross-sectional shape.
The ARC layer etch step 60 is followed by a fifteen second break through etch step 62, during which the flow of passivation gas is stopped. It is known in the art that the uppermost portion of a metal layer such as layer 16 will be more resistive to an etching process than will be the remainder of the layer. It is believed that a small amount of corrosion products may accumulate on the top surface of a metal layer during the processing of the device, thereby creating a thin interface layer 29, perhaps less than 100 Angstroms thick, that becomes more resistive to etching. Break through etch step 62 utilizes a significantly higher flow rate of BCl3 than the other etch steps. In addition, the bias power level 54 is also significantly increased to provide a higher energy level to the etching ions. Moreover, the flow of passivation gas is preferably stopped in order to improve the removal rate, to improve the control of the resulting geometry, and for chamber cleanliness considerations.
A main metal etch step 64 is then performed for a duration EP, which may be approximately 60 seconds for example, to remove the remaining thickness of the metal layer 16. Strategies for determining the appropriate time to end this step are well known in the art. Barrier etch step 66 and over-etch steps 68,70 are then conducted to remove the TiN and Ti layers 24,22 and to remove a small portion of the SiO2 layer.
As the densities of semiconductor devices continue to increase, the corresponding sizes of semiconductor structures continue to decrease. Designers of such devices prefer to decrease the thickness T of the photoresist layer 20 in order to facilitate the production of such small structures. However, if the thickness T is reduced to significantly less than one micron, subsequent control of photoresist erosion will result in the formation of a notch 32 in the interconnect 18, as is shown in FIG. 1. One skilled in the art may appreciate that the presence of notch 32 may be deleterious to the quality of device 10 by locally increasing the resistance of interconnect 18, thereby affecting the electromagnetic environment of the device and by increasing the heat generation in the interconnect 18 proximate the notch 32. It is also known that by maintaining the thickness T of photoresist layer 20 to be close to or greater than about one micron, the presence of notch 32 can be prevented by using recipe parameters that consume additional photoresist and thereby provide additional buffering material to the reactor environment. For example, maintaining the bias power at a higher level during the metal etch step 64 would reduce the notching effect however it would also increase the amount of photoresist removed during the main etch step. Accordingly, the designers of prior art devices 10 are forced to maintain the thickness T of photoresist layer 20 to a value greater than would otherwise be preferred in order to control the geometry of interconnect 18. Most prior art devices 10 are manufactured with a thickness T of photoresist layer 20 to be approximately one micron, and rarely with a thickness T of photoresist layer to be as low as 0.75 microns.
Accordingly, there is a particular need for a method of forming an interconnect without notching during the transition from a barrier layer etch step to a metal layer etch step. There is a further need to develop a process for metal layer etching that will yield a required slope in the sides of the etched layer without notching when the masking photoresist layer has a thickness of less than 0.75-1.00 micron.
Accordingly, a method for making a semiconductor device of the type having a metal layer disposed on a semiconductor layer is disclosed herein, the method comprising the steps of: exposing the metal layer to a reactive ion etch comprising a flow of etchant gas and a flow of passivation gas; and controlling the ratio of the flow rate of passivation gas to the flow rate of etchant gas to a first value during an initial period of the reactive ion etch and to a second value during a remainder of the reactive ion etch. The first value may be at least twice or at least thrice the second value.
A further method is disclosed herein for making a semiconductor device of the type having a metal layer disposed on a semiconductor layer, the metal layer having a top interface layer, the method comprising the steps of: exposing the metal layer to a reactive ion etch comprising a flow of etchant gas containing no passivation gas to remove the top interface layer; exposing the metal layer to a reactive ion etch comprising a flow of etchant gas containing a first concentration of passivation gas to remove a first portion of the metal layer; and exposing the metal layer to a reactive ion etch comprising a flow of etchant gas containing a second concentration of passivation gas to remove a second portion of the metal layer. The first concentration may be at least twice or at least thrice the second concentration. A further method is disclosed herein for making a semiconductor device of the type having a metal layer disposed on a semiconductor layer and protected by a patterned resist layer, the method comprising the steps of: exposing the metal layer to a reactive ion etch (RIE) to form a metal interconnect on the semiconductor layer by selectively removing portions of the metal layer not protected by the resist layer, the RIE further comprising: a burst etch step wherein a flow of passivation gas is provided at a first concentration with a flow of etchant gas; and a main etch step wherein a flow of passivation gas is provided at a second concentration with a flow of etchant gas. The first concentration may be at least twice or at least thrice the second concentration. The method may further comprises a break through step wherein a flow of etchant gas is provided without passivation gas to remove an interface layer portion of the metal layer prior to the burst etch step.
A product is disclosed herein formed by the process of: providing a semiconductor layer; forming a metal layer on the semiconductor layer; forming an anti-reflective coating layer on the metal layer; forming a patterned photoresist layer on the anti-reflective coating layer; conducting a reactive ion etch (RIE) process to form an interconnect on the semiconductor layer by removing portions of the ARC layer and metal layer exposed by the patterned photoresist layer, the RIE process further comprising: conducting an ARC etch step to remove portions of the anti-reflective coating layer; and conducting a metal etch step comprising a burst etch step followed by a main etch step, the burst etch step comprising providing a first concentration of passivation gas and the main etch step comprising providing a second concentration of passivation gas.